One of the challenges in integrated circuits (ICs) design and fabrication is to reduce resistive capacitive (RC) delay in signal transmission. Conventional methods for reducing the RC delay include replacing aluminum metal layer with copper metal layer to reduce series resistance of the metal layer. Conventional methods also include reducing the parasitic capacitance between metal layers by forming porous low dielectric constant (low-K) materials or air gaps in the dielectric layer between the metal layers.
For example, FIG. 1 depicts formation of an interconnect structure using a conventional method. As shown, a substrate 5 is provided having semiconductor devices formed therein. A low-K dielectric layer 4 is formed on the substrate 5. A mask layer 6 is formed on the low-K dielectric layer 4. The low-K dielectric layer 4 is then patterned using the mask layer 6 as a mask to form a through hole. A metal material is then used to fill the through hole to form a contact plug connected with the semiconductor devices. However, during practical fabrication processes, an undercut often occurs between the mask layer and the low-K dielectric layer in the interconnect structure.
FIG. 2 depicts a conventional interconnect structure having an undercut. In the fabrication process of the interconnect structure, after a low-K dielectric layer 11 is patterned by a wet etching using a hard mask 12 as a mask, an undercut 13 is formed at the interface between the low-K dielectric layer 11 and the hard mask 12. In some cases, the size of the undercut 13 can reach about 5 nm. The existence of the undercut 13 may cause problems including the stripping of the hard mask 12. This affects the fabrication yield of interconnect structures and even affects the reliability of interconnect structures.